Semiconductor chip, semiconductor device and manufacturing process for manufacturing the same

ABSTRACT

A semiconductor device includes a substrate main body, a plurality of first bump pads, and redistribution layer (RDL). The first bump pads are disposed adjacent to a surface of the substrate main body, each of the first bump pads has a first profile from a top view, the first profile has a first width along a first direction and a second width along a second direction perpendicular to the first direction, and the first width of the first profile is greater than the second width of the first profile. The RDL is disposed adjacent to the surface of the substrate main body, and the RDL includes a first portion disposed between two first bump pads.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to a semiconductor chip, a semiconductordevice and a manufacturing process for manufacturing the same, and moreparticularly to a semiconductor chip and a semiconductor device capableof routing a redistribution layer (RDL) under the semiconductor chip anda method for manufacturing the same.

2. Description of the Related Art

A conventional semiconductor package may include a substrate and asemiconductor chip disposed on the substrate. The substrate may includea RDL and bump pads. The semiconductor chip may include pillars bondedto the bump pads in a chip bonding area of the substrate. The RDL mayneed to bypass or be routed away from the chip bonding area, to avoidshort circuits between the RDL and bump pads in the chip bonding area.However, such configuration may lead to increased path length andincreased impedance in the RDL, and thus adversely affecting theperformance of the circuitry within the semiconductor package.

SUMMARY

In an aspect, a semiconductor chip includes a chip main body, at leastone first pillar and at least one second pillar. The first pillar isdisposed adjacent to a surface of the chip main body. The first pillarhas a first profile from a bottom view, the first profile has a firstwidth along a first direction and a second width along a seconddirection perpendicular to the first direction, and the first width ofthe first profile is greater than the second width of the first profile.The second pillar is disposed adjacent to the surface of the chip mainbody, the second pillar has a second profile from a bottom view, and ashape of the first profile is different from a shape of the secondprofile.

In an aspect, a semiconductor device includes a substrate main body, aplurality of first bump pads, and an RDL. The first bump pads aredisposed adjacent to a surface of the substrate main body, each of thefirst bump pads has a first profile from a top view, the first profilehas a first width along a first direction and a second width along asecond direction perpendicular to the first direction, and the firstwidth of the first profile is greater than the second width of the firstprofile. The RDL is disposed adjacent to the surface of the substratemain body, and the RDL includes a first portion disposed between twofirst bump pads.

In an aspect, a semiconductor device includes a substrate main body, achip bonding area on the substrate main body, and an RDL. The RDL isdisposed adjacent to a surface of the substrate main body. The RDLincludes a first portion disposed within the chip bonding area and asecond portion disposed outside the chip bonding area. A width of thefirst portion is less than a width of the second portion.

In an aspect, a manufacturing process includes (a) providing a substratemain body, the main body including pads adjacent to a surface thereof;(b) forming a photoresist layer adjacent to the surface of the substratemain body and covering the pads; (c) forming first openings and secondopenings in the photoresist layer to expose the pads, where a shape ofthe second openings is different from a shape of the first openings, anda cross-sectional area of each of the second openings is substantiallyequal to a cross-sectional area of each of the first openings; (d)filling the first openings and the second openings concurrently with ametal; and (e) removing the photoresist layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a bottom view of a semiconductor chip according to anembodiment of the present disclosure.

FIG. 2 illustrates an enlarged view of a region A1 shown in FIG. 1according to an embodiment of the present disclosure.

FIG. 3 illustrates a cross-sectional view of the region A1 shown in FIG.2 according to an embodiment of the present disclosure.

FIG. 4 illustrates a top view of a semiconductor device according to anembodiment of the present disclosure.

FIG. 5 illustrates an enlarged view of a region A4 shown in FIG. 4according to an embodiment of the present disclosure.

FIG. 6 illustrates a cross-sectional view of the region A4 shown in FIG.5 according to an embodiment of the present disclosure.

FIG. 7 illustrates a cross-sectional view of the region A4 shown in FIG.5 according to an embodiment of the present disclosure.

FIG. 8 illustrates a top view of a semiconductor package.

FIG. 9 illustrates a top view of a semiconductor device according to anembodiment of the present disclosure.

FIG. 10 illustrates an enlarged view of a region A9 shown in FIG. 9according to an embodiment of the present disclosure.

FIG. 11 illustrates a cross-sectional view of the region A9 shown inFIG. 10 according to an embodiment of the present disclosure.

FIG. 12 illustrates a cross-sectional view of the region A9 shown inFIG. 10 according to an embodiment of the present disclosure.

FIG. 13 illustrates a cross-sectional view of a semiconductor deviceaccording to an embodiment of the present disclosure.

FIG. 14 illustrates a cross-sectional view of a semiconductor deviceaccording to an embodiment of the present disclosure.

FIG. 15 illustrates a top view of a semiconductor device according to anembodiment of the present disclosure.

FIG. 16A, FIG. 16B, FIG. 16C and FIG. 16D illustrate a manufacturingprocess according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

The present disclosure provides an improved semiconductor packagestructure allowing for reduced circuit path length in an RDL.

Pillars of a semiconductor chip may be bonded to bump pads in a chipbonding area of a substrate, and a size and a position of each bump padin a chip bonding area may correspond to a size and a position of acorresponding pillar. A pitch between adjacent pillars may be small,and, correspondingly, a pitch between adjacent bump pads in the chipbonding area may also be small. Therefore, a gap between two adjacentbump pads in the chip bonding area may be small. If a portion of the RDLpasses through the gap, there is a risk of short circuit due to the RDLcontacting one or both of the bump pads. To address such concerns, theRDL may be designed to bypass or to be routed away from the bump pads inthe chip bonding area. However, such bypass or routing away maysignificantly increase a path length (and an impedance) of a circuitpath in the RDL. Consequently, such bypassed away or routed away designmay adversely affect a performance of circuitry within a semiconductorpackage.

To address the above concerns, an improved structure is formed thatprovides shorter path length (and lower impedance) of circuit paths inthe RDL, through improved pillar structure and bump pad structure. Thetechniques described may be helpful to yield circuitry with improvedperformance. The improved pillar structure provides for a wider gapbetween adjacent pillars, and the improved bump pad structure providesfor a wider gap between adjacent bump pads, so that a portion of the RDLcan pass through the gap space between the two adjacent bump padsdirectly rather than being bypassed away or routed away. The risk of ashort circuit is low because the portion of the RDL will not readilycontact one or both of the two bump pads.

FIG. 1 illustrates a bottom view of a semiconductor chip 10 according toan embodiment of the present disclosure. The semiconductor chip 10includes first pillars 101 and second pillars 102 for electricalconnections. The first pillar 101 has a first profile from the bottomview, and the second pillar 102 has a second profile from the bottomview, and a shape of the first profile is different from a shape of thesecond profile. In one or more embodiments, a shape of the first profileof the first pillar 101 is substantially elliptical, and a shape of thesecond profile of the second pillar 102 is substantially circular.

The first pillars 101 are arranged along a first direction D 1. Thefirst pillars 101 are arranged in an array, and the second pillars 102are arranged such that there is an array of the second pillars 102, witha subarray of the second pillars 102 on each of two sides of the arrayof the first pillars 101. In the embodiment of FIG. 1, there are tworows in the array of the first pillars 101, and each array of the secondpillars 102 is arranged in a ring-link structure. It is noted that a gapspace between the two rows of first pillars 101 corresponds to a portionof an RDL of a substrate.

A passivation layer 108 exposes the first pillars 101 and the secondpillars 102 from the bottom view illustrated in FIG. 1.

FIG. 2 illustrates an enlarged view of a region A1 of the semiconductorchip 10 shown in FIG. 1 according to an embodiment of the presentdisclosure. The first profile of the first pillar 101 has a first widthW₁ along the first direction D1 and a second width W₂ along a seconddirection D2 perpendicular to the first direction D1. The first width W₁of the first profile of the first pillar 101 is greater than the secondwidth W₂ of the first profile of the first pillar 101. In one or moreembodiments, the first width W₁ of the first profile of the first pillar101 is at least about 2 times greater, at least about 3 times greater,or about four to about nine times greater than the second width W₂ ofthe first profile of the first pillar 101. In other words, (W₁)>(n)(W₂),where, in some embodiments, 4≦n≦9. In the embodiment illustrated in FIG.2, the shape of the second profile of the second pillar 102 isapproximately circular and has a diameter W′. In other words, the secondprofile of the second pillar 102 has a diameter W′ along the firstdirection D1 and along the second direction D2. More generally, thesecond profile has a first width along the first direction D1 and asecond width along the second direction D2 perpendicular to the firstdirection, and the first width of the second profile is substantiallyequal to the second width of the second profile. In the embodiment shownin FIG. 2, the first width W₁ of the first profile of the first pillar101 is about two times the diameter W′ of the second pillar 102, and thesecond width W₂ of the first profile of the first pillar 101 is abouthalf of the diameter W′ of the second pillar 102. Thus, in thisembodiment, the first width W₁ of the first profile of the first pillar101 is approximately four times the second width W₂ of the first profileof the first pillar 101. In some embodiments, an area of the firstprofile of the first pillar 101 is substantially equal to an area of thesecond profile of the second pillar 102.

Referring back to FIG. 1, it is noted that a pitch between adjacentfirst pillars 101 may be similar to, or may be different from, a pitchbetween adjacent second pillars 102. It is further noted that a pitchbetween a first pillar 101 and an adjacent second pillar 102 may besimilar to, or may be different from, the pitch between adjacent firstpillars 101 or the pitch between adjacent second pillars 102.

FIG. 3 illustrates a cross-sectional view taken along line 3-3 of FIG.2. The semiconductor chip 10 includes a chip main body 106, the firstpillars 101, the second pillars 102, first pillar pads 103, secondpillar pads 104 and a passivation layer 108. The chip main body 106 hasa first surface 106 a. The first pillars 101 and the second pillars 102are disposed adjacent to the first surface 106 a of the chip main body106. In the embodiment illustrated in FIG. 3, the first pillar pads 103,the second pillar pads 104 and the passivation layer 108 are disposed onthe first surface 106 a of the chip main body 106. The passivation layer108 covers the first surface 106 a of the chip main body 106, andpartially covers the first pillar pads 103 and the second pillar pads104 to form a plurality of openings on respective ones of the firstpillar pads 103 and the second pillar pads 104. The first pillars 101and the second pillars 102 are disposed in the openings corresponding tothe first pillar pads 103 and the second pillar pads 104, respectively.

Each of the first pillars 101 has the second width W₂, and each of thesecond pillars 102 has a diameter W′. In one or more embodiments, thesecond width W₂ of the first pillars 101 is less than the diameter W′ ofthe second pillars 102. For example, the second width W₂ of the firstpillars 101 is, but is not limited to, about half of the diameter W′ ofthe second pillars 102. In one or more embodiments, a cross-sectionaldimension of the first pillar pad 103 corresponding to the first pillar101 is less than a cross-sectional dimension of the second pillar pad104 corresponding to the second pillar 102. In other embodiments,cross-sectional dimensions of the first pillar pads 103 and the secondpillar pads 104 may be similar.

FIG. 4 illustrates a top view of a semiconductor device 4 according toan embodiment of the present disclosure. The semiconductor device 4 maybe a substrate or an interposer, and includes a substrate main body 46,bump pads 40, bonding pads 44, one or more chip bonding areas C1, C2,and an RDL 47. The bump pads 40, the bonding pads 44, the chip bondingareas C1, C2, and the RDL 47 are disposed on or adjacent to a surface 46a of the substrate main body 46.

Each bump pad 40 has approximately a same shape from the top view, andeach bump pad 40 is approximately circular with approximately a samediameter as the others of the bump pads 40. The bump pads 40 areprovided for bumps to be disposed thereon, to connect to respectivepillars of a semiconductor chip. As shown in FIG. 4, the bump pads 40are arranged in an array, with a subarray of the bump pads 40 arrangedin the chip bonding area C1, and a subarray of the bump pads 40 arrangedin the chip bonding area C2. A virtual perimeter around an outermostring of a group of the bump pads 40 on one side of the semiconductordevice 40 outlines the chip bonding area C1, and another virtualperimeter around another outermost ring of another group of the bumppads 40 on the other side of the semiconductor device 40 outlines thechip bonding area C2. An area within the virtual perimeter of each ofthe chip bonding areas C1, C2 is substantially equal to a surface areaof a corresponding semiconductor chip.

The bonding pads 44 are provided for interconnection elements (e.g.,solder balls) to be disposed thereon; for example, to connect to amother board. The bonding pads 44 are disposed at a periphery of thesubstrate main body 46 and surround the bump pads 40. Dimensions of thebonding pads 44 are greater than corresponding dimensions of the bumppads 40 (in the top view).

The RDL 47, the bump pads 40 and the bonding pads 44 may be formedduring a same process stage (e.g., in a same plating and etching stage).The RDL 47, the bump pads 40 and the bonding pads 44 are in a samelayer, are parts of a patterned circuit layer, and are made of a samematerial (e.g., copper). The RDL 47 connects the bump pads 40 to eachother, the bonding pads 44 to each other, and/or the bump pads 40 to thebonding pads 44.

In the embodiment illustrated in FIG. 4, the RDL 47 includes a firstportion 47A, a second portion 47B, a third portion 47C and a fourthportion 47D. The first portion 47A is disposed within the chip bondingarea C1 and between two rows of the bump pads 40. That is, the firstportion 47A is disposed at a gap between two rows of the bump pads 40.Thus, the first portion 47A of the RDL 47 extends through the chipbonding area C1, and is parallel with a first direction D1. The firstportion 47A is physically connected to an electrical element outside thechip bonding area C1. In one or more embodiments, the electrical elementis a bonding pad 44, the second portion 47B of the RDL 47, or a bump pad40 in another chip bonding area (e.g., C2). It is noted that theelectrical element and the RDL 47 are part of a same layer.

The second portion 47B of the RDL 47 is disposed outside the chipbonding area C1, and physically connects the first portion 47A and thebonding pad 44, or the first portion 47A and the third portion 47C. Thethird portion 47C is disposed within the chip bonding area C1 andphysically connects two bump pads 40. The fourth portion 47D physicallyconnects the bump pad 40 and the bonding pad 44. In one or moreembodiments, widths of the second portion 47B, the third portion 47C andthe fourth portion 47D are substantially the same; and a width of thefirst portion 47A is less than a width of the second portion 47B. Thesegment of the RDL 47 including the first portion 47A and the secondportion 47B is substantially straight. The direct connection path of thefirst portion 47A and the second portion 47B passes through the gapbetween the two rows of the bump pads 40 without bypassing or routingaway from the chip bonding area C1. In addition, because the width ofthe first portion 47A is less than the width of the second portion 47B,a risk of short circuit is low because the first portion 47A of the RDL47 will not generally contact one or both of the two rows of the bumppads 40. Therefore, a length of a circuit path of the RDL 47 (and itsimpedance) can be significantly reduced. In other words, this embodimentis beneficial to yield a performance-improved circuitry.

FIG. 5 illustrates an enlarged view of a region A4 of the semiconductordevice 4 shown in FIG. 4 according to an embodiment of the presentdisclosure. The third portion 47C connecting two bump pads 40 has awidth L, the first portion 47A has a width L₁, and the second portion47B has a width L₂. In one or more embodiments, the width L of the thirdportion 47C is substantially equal to the width L₂ of the second portion47B, and the width L₁ of the first portion 47A is about half of thewidth L₂ of the second portion 47B. In other embodiments, the width L₁of the first portion 47A is about ⅓ of the width L₂ of the secondportion 47B. Further embodiments vary the widths L, L₁ and L₂ withrespect to each other.

FIG. 6 illustrates a cross-sectional view taken along line 6-6 of FIG.5. As shown in FIG. 6, the semiconductor device 4 comprises thesubstrate main body 46, the bump pads 40 and the RDL 47. The bump pads40 and the RDL 47 are disposed adjacent to the surface 46 a of thesubstrate main body 46. The RDL 47 includes the first portion 47Adisposed between two bump pads 40. As shown in FIG. 6, the width L₁ ofthe first portion 47A of the RDL 47 is about one third of a diameter W₃of each of the bump pads 40. In one or more embodiments, the width L₁ ofthe first portion 47A may be, but is not limited to, about one half ofto about one quarter of the diameter W₃ of each of the bump pads 40. Inaddition, a pitch W_(X) between two adjacent bump pads 40 without thefirst portion 47A between is substantially the same as the pitch W_(X)between two adjacent bump pads 40 with the first portion 47A between.Thus, the RDL 47 may be routed between the bump pads 40.

FIG. 7 illustrates a cross-sectional view of the semiconductor device 4of FIG. 6 according to an embodiment of the present disclosure, in whicha protection layer 48 is disposed over the surface 46 a of the substratemain body 46, and bumps 43 are disposed over respective bump pads 40.The protection layer 48 covers the surface 46a of the substrate mainbody 46 and the RDL 47, and partially covers the bump pads 40 to form aplurality of openings over respective ones of the bump pads 40. Thebumps 43 are disposed in the openings corresponding to the bump pads 40.The bumps 43 are cylindrical. The sizes and positions of the bumps 43correspond to the sizes and positions of the bump pads 40. Thus, becausethe pitch W_(X) between two adjacent bump pads 40 is consistent(approximately the same) for each pair of adjacent bump pads 40, a pitchbetween each pair of adjacent bumps 43 can also be consistent(approximately the same) when bumps 43 are positioned on all of the bumppads 40. Note that, in FIG. 4, there are areas void of the bump pads 40;the term “adjacent” with respect to pairs of the bump pads 40 or pairsof the bumps 43 does not include pairs spanning such a void area.

FIG. 8 illustrates a circuit design from top view by way of comparison.The circuit design of FIG. 8 includes a chip bonding area C3, bump pads40a, and a portion 49A of an RDL 49. The circuit design of FIG. 8 doesnot allow routing of the RDL between bump pads 40 a. Dimensions of thechip bonding area C3 are approximately the same as the dimensions of thechip bonding area C1 or C2 of FIG. 4. The bump pads 40 a are disposedwithin the chip bonding area C3. The portion 49A of the RDL 49 has aconsistent width, and the width of the portion 49A of the RDL 49 in FIG.8 is same as the width of the second portion 47B of the RDL 47 in FIG.4. The portion 49A of the RDL 49 in FIG. 8 is disposed outside the chipbonding area C3 and is routed around the chip bonding area C3.

For purposes of comparison, in an example of the circuit design of FIG.8, a width of the chip bonding area C3 is about 7 millimeters (mm), thewidth of the portion 49A is about 20 micrometers (μm), a thickness ofthe portion 49A is about 3 μm, a length of the portion 49A from a pointP3 to a point P4 is about 20.7 mm, and a resistance of the portion 49Afrom the point P3 to the point P4 is about 5.8 Ohm.

In comparison, for an example of the embodiment of FIG. 4, a width ofthe chip bonding area C1 is about 7 mm (akin to the width of the chipbonding area C3 of FIG. 8), the width L₂ of the second portion 47B isabout 20 μm (akin to the width of the portion 49A of FIG. 8), and athickness of the segment including the first portion 47A and the secondportion 47B is about 3 μm (akin to the thickness of the portion 49A ofFIG. 8). However, the width L₁ of the first portion 47A is about 10 μm,a length of the segment from a point P1 to a point P2 is about 11.2 mm,and a resistance of the segment from point P1 to point P2 is about 5.26Ohm. As compared with FIG. 8, it would be understood that theconfiguration according to the embodiment of FIG. 4 can lower aresistance between two points by reducing a path length in the RDL.

FIG. 9 illustrates a top view of a semiconductor device 5 according toan embodiment of the present disclosure. The semiconductor device 5 ofFIG. 9 is similar to the semiconductor device 4 illustrated in FIG. 4, adifference being that, in FIG. 9, bumps pads 40 include first bump pads401 and second bump pads 402, and a width of a first portion 47A of anRDL 47 is substantially equal to a width of a second portion 47B of anRDL 47.

The first bump pad 401 has a first profile from the top view, and thesecond bump pad 402 has a second profile from the top view, and a shapeof the first profile is different from a shape of the second profile (anexample is provided with respect to FIG. 10). The first and second bumppads 401 and 402 are provided for bumps to be disposed thereon, toconnect to pillars of a semiconductor chip. As shown in FIG. 9, the bumppads 40 are arranged in an array, with a subarray of the bump pads 40arranged in the chip bonding area C1, and a subarray of the bump pads 40arranged in the chip bonding area C2. A virtual perimeter around anoutermost ring of a group of the bump pads 40 on one side of thesemiconductor device 40 outlines the chip bonding area C1, and anothervirtual perimeter around another outermost ring of another group of thebump pads 40 on the other side of the semiconductor device 40 outlinesthe chip bonding area C2. An area within the virtual perimeter of eachof the chip bonding areas C1, C2 is substantially equal to a surfacearea of a corresponding semiconductor chip.

Bonding pads 44 are provided for interconnection elements (e.g., solderballs) to be disposed thereon; for example, to connect to a motherboard. The bonding pads 44 are disposed at a periphery of a substratemain body 46 and surround the bump pads 40. Dimensions of the bondingpads 44 are greater than corresponding dimensions of the bump pads 40(in the top view).

The RDL 47, the bump pads 40 and the bonding pads 44 may be formedduring a same process stage (e.g., in a same plating and etching stage).The RDL 47, the bump pads 40 and the bonding pads 44 are in a samelayer, are parts of a patterned circuit layer, and are made of a samematerial (e.g., copper). The RDL 47 connects the bump pads 40 to eachother, the bonding pads 44 to each other, and/or the bump pads 40 to thebonding pads 44.

In the embodiment illustrated in FIG. 9, the RDL 47 includes a firstportion 47A, a second portion 47B, a third portion 47C and a fourthportion 47D. The first portion 47A is disposed within the chip bondingarea C1 and between two rows of the first bump pads 401. That is, thefirst portion 47A is disposed at a gap between two rows of the firstbump pads 401. Thus, the first portion 47A of the RDL 47 extends throughthe chip bonding area C1, and is parallel with a first direction D1. Thefirst portion 47A is physically connected to an electrical elementoutside the chip bonding area C1. In one or more embodiments, theelectrical element is a bonding pad 44, the second portion 47B of theRDL 47, a first bump pad 401 or a second bump pad 402 in another chipbonding area (e.g., C2). It is noted that the electrical element and theRDL 47 are part of a same layer.

The second portion 47B of the RDL 47 is disposed outside the chipbonding area C1, and physically connects the first portion 47A and thebonding pad 44, or the first portion 47A and the third portion 47C. Thethird portion 47C is disposed within the chip bonding area C1, andphysically connects the first bump pad 401 and the second bump pad 402.The fourth portion 47D physically connects the second bump pad 402 andthe bonding pad 44. In one or more embodiments, widths of the firstportion 47A, the second portion 47B, the third portion 47C and thefourth portion 47D are substantially the same. A segment of the RDL 47including the first portion 47A and the second portion 47B issubstantially straight. The direct connection path of the first portion47A and the second portion 47B passes through the gap between the tworows of the first bump pads 401 without bypassing or routing away fromthe chip bonding area C1. In addition, because a width of the first bumppads 401 in a direction D2 is less than the width of the bump pads 402in the direction D2, a risk of short circuit is low because the firstportion 47A of the RDL 47 will not generally contact one or both of thetwo rows of the first bump pads 401. Therefore, a length of a circuitpath of the RDL 47 (and its impedance) can be significantly reduced. Inother words, this embodiment is beneficial to yield aperformance-improved circuitry.

FIG. 10 illustrates an enlarged view of a region A9 of the semiconductordevice 5 shown in FIG. 9 according to an embodiment of the presentdisclosure. In this embodiment, a shape of a first profile of the firstbump pads 401 is substantially elliptical, and a shape of a secondprofile of the second bump pads 402 is substantially circular. The firstprofile of the first bump pad 401 has a first width W₄ along the firstdirection D1 and a second width W₅ along a second direction D2perpendicular to the first direction D1. The first width W₄ of the firstprofile of the first bump pad 401 is greater than the second width W₅ ofthe first profile of the first bump pad 401. In one or more embodiments,the first width W₄ of the first profile of the first bump pad 401 is atleast about 2 time greater, at least about 3 times greater, or aboutfour to about nine times greater than the second width W₅ of the firstprofile of the first bump pad 401. In other words, (W₄)>(n)(W₅), where,in some embodiments, 4≦n≦9.

In the embodiment illustrated in FIG. 10, the shape of the secondprofile of the second bump pad 402 is approximately circular with adiameter W. More generally, the second profile has a first width alongthe first direction D1 and a second width along the second direction D2perpendicular to the first direction, and the first width of the secondprofile is substantially equal to the second width of the secondprofile. As shown in FIG. 10, the first width W₄ of the first profile ofthe first bump pad 401 is about two times the diameter W of the secondprofile of the second bump pad 402, and the second width W₅ of the firstprofile of the bump pad 401 is about one half of the diameter W of thesecond profile of second bump pad 402. In this embodiment, the firstwidth W₄ of the first profile of the first bump pad 401 is about fourtimes the second width W₅ of the first profile of the first bump pad401. Other relative dimensions are contemplated for other embodiments.In one or more embodiments, an area of the first profile of the firstbump pad 401 is substantially equal to an area of the second profile ofthe second bump pad 402. In one or more embodiments, a pitch betweenadjacent first bump pads 401 is consistent (each pair of adjacent firstbump pads 401 has approximately a same pitch), and a pitch betweenadjacent second bump pads 402 is consistent (each pair of adjacentsecond bump pads 402 has approximately a same pitch). In one or moreembodiments, a pitch between an adjacent first bump pad 401 and secondbump pad 402 is consistent (each pair of a first bump pad 401 adjacentto a second bump pad 402 has approximately a same pitch). It is notedthat the pitch between adjacent first bump pads 401, the pitch betweenadjacent second bump pads 402, and the pitch between an adjacent firstbump pad 401 and second bump pad 402 may be approximately the same, ormay be different.

FIG. 11 illustrates a cross-sectional view taken along line 11-11 ofFIG. 10. As shown in FIG. 11, the semiconductor device 5 includes thesubstrate main body 46, the first bump pads 401, the second bump pads402, and the RDL 47. The first bump pads 401, the second bump pads 402and the RDL 47 are disposed adjacent to a surface 46a of the substratemain body 46. The RDL includes the first portion 47A disposed betweentwo first bump pads 401. In addition, a pitch W_(X) between two adjacentbump pads 40 (bump pads 401 or 402) without the first portion 47Abetween is substantially the same as the pitch W_(X) between twoadjacent bump pads 40 (bump pads 401) with the first portion 47Abetween. Thus, the RDL may be routed between the bump pads 40.

FIG. 12 illustrates a cross-sectional view of the semiconductor device 5of FIG. 11 according to an embodiment of the present disclosure, inwhich a protection layer 48 is disposed over the surface 46 a of thesubstrate main body 46, and bumps 43 are disposed over respective bumppads 40. The bumps 43 include first bumps 431 disposed over respectivebump pads 401 and second bumps 432 disposed over respective bump pads402. The protection layer 48 covers the surface 46 a of the substratemain body 46 and the RDL 47, and partially covers the bump pads 40 (thefirst bump pads 401 and the second bump pads 402) to form a plurality ofopenings over respective ones of the bump pads 40. The bumps 43 aredisposed in the openings corresponding to the bump pads 40. The firstbumps 431 and the second bumps 432 are disposed in the openingscorresponding to the first bumps pads 401 and the second bump pads 402,respectively. The bumps 43 are cylindrical. The sizes and positions ofthe bumps 43 correspond to the sizes and positions of the bump pads 40.Thus, if the pitch W_(X) between two adjacent bump pads 40 is consistent(approximately the same) for each pair of adjacent bump pads 40, a pitchbetween each pair of adjacent bumps 43 can also be consistent(approximately the same) when bumps 43 are positioned on all of the bumppads 40. Note that, in FIG. 9, there are areas void of the bump pads 40;the term “adjacent” with respect to pairs of the bump pads 40 or pairsof the bumps 43 does not include pairs spanning such a void area.

As shown in FIGS. 9-12, the first portion 47A of the RDL 47 extendsthrough the gap between two rows of the first bump pads 401 (as shown inFIG. 9). Such a direct connection path through the gap space between twofirst bump pads 401 avoids bypassing or routing away from the chipbonding area C1 (as shown in FIG. 9). In addition, because the width ofthe first bump pads 401 in the direction D2 is less than the width ofthe second bump pads 402 in the direction D2, a risk of short circuit islow because the first portion 47A of the RDL 47 will not generallycontact one or both of the two rows of the bump pads 401. Therefore, alength of a circuit path of the RDL 47 (and its impedance) can besignificantly reduced. In other words, this embodiment is beneficial toyield a performance-improved circuitry.

FIG. 13 illustrates a cross-sectional view of a semiconductor device 130according to an embodiment of the present disclosure. The semiconductordevice 130 may be a package, and includes a semiconductor chip 10 (asshown in FIG. 3) and a semiconductor device 5 (as shown in FIG. 12). InFIG. 13, the first pillars 101 of the semiconductor chip 10 arephysically connected to the first bumps 431 of the semiconductor device5, and the second pillars 102 of the semiconductor chip 10 arephysically connected to the second bumps 432 of the semiconductor device5. In the embodiment illustrated in FIG. 13, the second width W₂ of thefirst pillar 101 (refer to FIG. 2) and a corresponding width of thefirst bump 431 are substantially the same, and the diameter W′ of thesecond pillar 102 (refer to FIG. 2) and a corresponding width of thesecond bump 432 are substantially the same. As can be seen in FIG. 13,the first portion 47A of the RDL 47 is routed under the semiconductorchip 10.

FIG. 14 illustrates a cross-sectional view of a semiconductor device 140according to an embodiment of the present disclosure. The semiconductordevice 140 of FIG. 14 is similar to the semiconductor device 130illustrated in FIG. 13, and the semiconductor device 140 furthercomprises a mother board 200 and at least one interconnection element210. The interconnection element(s) 210 connect the mother board 200 andrespective bonding pad(s) 44 of the semiconductor device 5 (FIG. 9). Themother board 200 may be, for example, a printed circuit board (PCB), andthe interconnection element 210 may be a solder ball.

FIG. 15 illustrates a top view of a semiconductor device 5 a accordingto an embodiment of the present disclosure. Similarly numbered featuresin FIG. 15 and FIG. 9 refer to similar components. The semiconductordevice 5 a is a substrate, and includes the first bump pads 401, thesecond bump pads 402, the fourth portion 47D of the RDL 47, and thebonding pads 44. The first bump pads 401 and the second bump pads 402are arranged in two subarrays to define two chip bonding areas C3 andC4. In the embodiment illustrated in FIG. 15, the first bump pads 401are arranged along the second direction D2, the width of the first bumppads 401 along direction D2 is greater than the width of the first bumppads 401 along direction D1, and the fourth portion 47D of the RDL 47 isparallel with the second direction D2.

One end of the fourth portion 47D of the RDL 47 is connected to a secondbump pad 402 within the chip bonding areas C3, C4, and the other end ofthe fourth portion 47D of the RDL 47 is connected to an electricalelement outside the chip bonding areas C3, C4. In one or moreembodiments, the electrical element is a bonding pad 44, another portionof the RDL 47, or a bump pad 40 in another chip bonding area (e.g., inthe other of the chip bonding areas C3, C4). The arrangement of thefirst bump pads 401 provides for a wider gap between the first bump pads401, so that the fourth portion 47D of the RDL 47 can pass through thegap between the two adjacent first bump pads 401 directly. Accordingly,the fourth portion 47D of the RDL 47 can be routed under a semiconductorchip.

FIGS. 16A-16D illustrate a manufacturing process according to anembodiment of the present disclosure. In this embodiment, themanufacturing process is used to manufacture the semiconductor device 5as shown in FIG. 12. However, the manufacturing process may also be usedto manufacture the semiconductor chip 10 as shown in FIG. 1 to FIG. 3.Referring to FIG. 16A, the semiconductor device 5 as shown in FIG. 11 isprovided. The semiconductor device 5 includes a protection layer 48disposed over the surface 46 a of the substrate main body 46. Theprotection layer 48 covers the surface 46 a of the substrate main body46 and the RDL 47, and partially covers the first bump pads 401 and thesecond bump pads 402 to form openings exposing respective ones of thefirst bumps pads 401 and the second bump pads 402. A photoresist layer50 is formed over the protection layer and the exposed first bump pads401 and second bump pads 402. In some embodiments, the protection layer48 is omitted, and the photoresist layer 50 is formed over the surface46a and over the first bumps pads 401 and the second bump pads 402.

Referring to FIG. 16B, first openings 501 and second openings 502 areformed in the photoresist layer 50. The first openings 501 and thesecond openings 502 extend through the photoresist layer 50 to exposethe first bumps pads 401 the second bumps pads 402, respectively. Thatis, the position of the first openings 501 and the second openings 502correspond to respective first bumps pads 401 and second bumps pads 402.

Referring to FIG. 16C, a top view of a partial area of the photoresistlayer 50 of FIG. 16B is shown. In FIG. 16C, each of the first openings501 defines a first profile, and each of the second openings 502 definesa second profile. The first profile of the first openings 501 has afirst width W₆ along a first direction D1 and a second width W₇ along asecond direction D2 perpendicular to the first direction D1. The firstwidth W₆ of the first profile of the first opening 501 is greater thanthe second width W₇ of the first profile of the first opening 501. Inone or more embodiments, the first width W₆ of the first profile of thefirst opening 501 is greater than the second width W₇ of the firstprofile of the first opening 501 by at least about 2 times, at leastabout 3 times, or about four to about nine times. In other words,(W₆)>(n)(W₇), where, in some embodiments, 4<n<9. In the embodimentillustrated in FIG. 16C, the shape of the second profile of the secondopening 502 is circular and has a diameter W″. Referring to FIG. 16C andFIG. 10, the first width W₆ of the first profile of the first opening501 may be substantially equal to the first width W₄ of the firstprofile of the first bump pad 401, the second width W₇ of the firstprofile of the first opening 501 may be substantially equal to thesecond width W₅ of the first profile of the first bump pad 401, and thediameter W″ of the second profile of the second opening 502 may besubstantially equal to the diameter W of the second profile of thesecond bump pad 402.

In one or more embodiments, the first width W₆ of the first profile ofthe first opening 501 is about two times the diameter W″ of the secondprofile of the second opening 502, and the second width W₇ of the firstprofile of the first opening 501 is about half of the diameter W″ of thesecond profile of second opening 502. Thus, in this embodiment, thefirst width W₆ of the first profile of the first opening 501 is aboutfour times the second width W₇ of the first profile of the first opening501. Different relative dimensions are contemplated for otherembodiments. As shown in FIG. 16B, heights of the first opening 501 andthe second opening 502 are substantially the same. In one or moreembodiments, an area of the first profile of the first opening 501 issubstantially equal to an area of the second profile of the secondopening 502; thus, volumes of the first opening 501 and the secondopening 502 are substantially the same.

Referring to FIG. 16D, the first openings 501 and the second openings502 are filled in a same process stage by a metal material (e.g.,copper) to form the first bumps 431 (see FIG. 12) in the first openings501 and the second bumps 432 (see FIG. 12) in the second openings 502,or to form the first pillars 101 (see FIG. 3) in the first openings 501and the second pillars 102 (see FIG. 3) in the second openings 502. Inan embodiment in which the volumes of the first opening 501 and thesecond opening 502 are substantially the same, the first opening 501 andthe second opening 502 may be filled concurrently (e.g., using oneelectroplating stage), which simplifies the manufacturing process. Incomparison, multiple electroplating stages may be needed if the bumpshad different cross-sectional areas (e.g., openings in the photoresistlayer with small diameter are filled using a first electroplating, andthen a second electroplating fills openings of the photoresist layerwith greater diameter).

After filling the first openings 501 and the second openings 502, thephotoresist layer 50 is removed to obtain the semiconductor device 5shown in FIG. 12.

Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,”“down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,”“lower,” “upper,” “over,” “under,” and so forth, are indicated withrespect to the orientation shown in the figures unless otherwisespecified. It should be understood that the spatial descriptions usedherein are for purposes of illustration only, and that practicalimplementations of the structures described herein can be spatiallyarranged in any orientation or manner, provided that the merits ofembodiments of this disclosure are not deviated by such arrangement.

As used herein, the terms “approximately,” “substantially,”“substantial” and “about” are used to describe and account for smallvariations. When used in conjunction with an event or circumstance, theterms can refer to instances in which the event or circumstance occursprecisely as well as instances in which the event or circumstance occursto a close approximation. For example, when used in conjunction with anumerical value, the terms can refer to a range of variation of lessthan or equal to ±10% of that numerical value, such as less than orequal to ±5%, less than or equal to ±4%, less than or equal to ±3%, lessthan or equal to ±2%, less than or equal to ±1%, less than or equal to±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. Foranother example, two numerical values can be deemed to be“substantially” the same if a difference between the values is less thanor equal to ±10% of an average of the values, such as less than or equalto ±5%, less than or equal to ±4%, less than or equal to ±3%, less thanor equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%,less than or equal to ±0.1%, or less than or equal to ±0.05%.

Additionally, amounts, ratios, and other numerical values are sometimespresented herein in a range format. It is to be understood that suchrange format is used for convenience and brevity and should beunderstood flexibly to include numerical values explicitly specified aslimits of a range, but also to include all individual numerical valuesor sub-ranges encompassed within that range as if each numerical valueand sub-range is explicitly specified.

While the present disclosure has been described and illustrated withreference to specific embodiments thereof, these descriptions andillustrations do not limit the present disclosure. It should beunderstood by those skilled in the art that various changes may be madeand equivalents may be substituted without departing from the truespirit and scope of the present disclosure as defined by the appendedclaims. The illustrations may not be necessarily drawn to scale. Theremay be distinctions between the artistic renditions in the presentdisclosure and the actual apparatus due to manufacturing processes andtolerances. There may be other embodiments of the present disclosurewhich are not specifically illustrated. The specification and drawingsare to be regarded as illustrative rather than restrictive.Modifications may be made to adapt a particular situation, material,composition of matter, method, or process to the objective, spirit andscope of the present disclosure. All such modifications are intended tobe within the scope of the claims appended hereto. While the methodsdisclosed herein have been described with reference to particularoperations performed in a particular order, it will be understood thatthese operations may be combined, sub-divided, or re-ordered to form anequivalent method without departing from the teachings of the presentdisclosure. Accordingly, unless specifically indicated herein, the orderand grouping of the operations are not limitations of the presentdisclosure.

1. A semiconductor chip, comprising: a chip main body; at least onefirst pillar disposed adjacent to a surface of the chip main body,wherein the first pillar has a first profile from a bottom view, thefirst profile has a first width along a first direction and a secondwidth along a second direction perpendicular to the first direction, andthe first width of the first profile is greater than the second width ofthe first profile; and at least one second pillar disposed adjacent tothe surface of the chip main body, wherein the second pillar has asecond profile from a bottom view, and a shape of the first profile isdifferent from a shape of the second profile.
 2. The semiconductor chipof claim 1, wherein the at least one first pillar is a plurality offirst pillars arranged along the first direction.
 3. The semiconductorchip of claim 1, wherein the at least one second pillar is a pluralityof second pillars arranged in an array.
 4. The semiconductor chip ofclaim 1, wherein an area of the first profile is substantially equal toan area of the second profile.
 5. The semiconductor chip of claim 1,wherein the second profile has a first width along the first directionand a second width along the second direction perpendicular to the firstdirection, and the first width of the second profile is substantiallyequal to the second width of the second profile.
 6. The semiconductorchip of claim 5, wherein the first width of the first profile is abouttwo times the first width of the second profile, and the second width ofthe first profile is about half of the second width of the secondprofile.
 7. A semiconductor device, comprising: a substrate main body; aplurality of first bump pads disposed adjacent to a surface of thesubstrate main body, each of the first bump pads has a first profilefrom a top view, the first profile has a first width along a firstdirection and a second width along a second direction perpendicular tothe first direction, and the first width of the first profile is greaterthan the second width of the first profile; and a redistribution layerdisposed adjacent to the surface of the substrate main body, wherein theredistribution layer includes a first portion disposed between two firstbump pads.
 8. The semiconductor device of claim 7, further comprising achip bonding area on the substrate main body and an electrical elementoutside the chip bonding area, the first portion of the redistributionlayer is disposed within the chip bonding area, and the first portion ofthe redistribution layer is physically connected to the electricalelement outside the chip bonding area.
 9. The semiconductor device ofclaim 8, wherein a virtual perimeter around an outermost ring of a groupof the first bump pads outlines the chip bonding area.
 10. Thesemiconductor device of claim 8, wherein the first portion of theredistribution layer extends through the chip bonding area.
 11. Thesemiconductor device of claim 8, wherein the chip bonding area is afirst chip bonding area, the semiconductor device further comprising asecond chip bonding area on the substrate main body, and wherein theelectrical element is a bonding pad, a second portion of theredistribution layer, or a bump pad in the second chip bonding area, andthe electrical element and the redistribution layer are in a same layer.12. The semiconductor device of claim 7, further comprising a pluralityof bumps disposed on the first bump pads.
 13. The semiconductor deviceof claim 7, wherein the first bump pads are arranged along the firstdirection, and the first portion of the redistribution layer is parallelwith the first direction.
 14. The semiconductor device of claim 7,further comprising a plurality of second bump pads, each of the secondbump pads has a second profile from a top view, and a shape of thesecond profile is different from a shape of the first profile, and anarea of the first profile is substantially equal to an area of thesecond profile.
 15. The semiconductor device of claim 14, wherein thefirst width of the first profile is about two times a first width of thesecond profile, and the second width of the first profile is about halfof a second width of the second profile.
 16. The semiconductor device ofclaim 14, further comprising a semiconductor chip bonded to the firstbump pads, the second bump pads, or the first bump pads and the secondbump pads.
 17. The semiconductor device of claim 7, further comprising amother board and at least one interconnection element, wherein theinterconnection element connects the mother board and the substrate mainbody. 18.-20. (canceled)
 21. A semiconductor device, comprising: asubstrate main body having a surface, the substrate main body includinga plurality of pads adjacent to the surface of the substrate main body;and a plurality of first metal bumps having a first profile from a topview and a plurality of second metal bumps having a second profile froma top view disposed on the pads; wherein the first profile of the firstmetal bumps is different from the second profile of the second metalbumps, and a cross-sectional area of each of the second metal bumps issubstantially equal to a cross-sectional area of each of the first metalbumps.
 22. The semiconductor device of claim 21, wherein the firstprofile has a first width along a first direction and a second widthalong a second direction perpendicular to the first direction, the firstwidth of the first profile is greater than the second width of the firstprofile; and wherein the second profile has a first width along thefirst direction and a second width along the second directionperpendicular to the first direction, and the first width of the secondprofile is substantially equal to the second width of the secondprofile.
 23. The semiconductor device of claim 21, further comprising: aredistribution layer disposed adjacent to the surface of the substratemain body, wherein the redistribution layer includes a first portionpassing through a gap space between two pads of the plurality of pads.